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MK1492-03 I C R O C LOC K Intel TM Mobile/SDRAM Clock Source
Description
The MK1492-03 is a low cost, low jitter, high performance clock synthesizer for Intel's 430TX and 440BX chipsets for PentiumTM and Pentium II Processor based computer applications. Using patented analog Phase-Locked Loop (PLL) techniques, the device accepts a 14.318 MHz crystal input to produce multiple output clocks up to 75 MHz. It provides selectable Host and Host/2 PCI local bus clocks and a selectable 24/48 MHz clock for Super I/O or Universal Serial Bus (USB). The device has up to eight Host output clocks, and includes a serial port for controlling the output clocks. The chip has three different power down modes to reduce power consumption.
VDD HOST3, 4
PRELIMINARY INFORMATION
Features
* I2C Serial Port for ACPI support * Packaged in 28 pin, 150 mil wide SSOP * Provides all critical timing for Intel mobile chipsets * Separate VDD and auto adjust for Host 1,2 supports 3.3 V or 2.5V processors * 48MHz USB or 24MHz SIO support * Single pin CPU(Host) slowdown to 33.3MHz option * Multiple power down modes * Low EMI Enable pin reduces EMI radiation on HOST and PCI clocks (patented) * Selectable PCIF on up to 3 outputs * Support for AC97 audio clocks
Block Diagram
VDD GND
DS
VDD HOST1, 2
CPU Slow/Stop Select PCI Free Run Enable CPU Frequency Select Low EMI Enable CPUS# PCISTP#
Output Buffers
HOST/PCI Clocks
2 HOST1,2 2 HOST3, 4 2 HOST 5:8 4 PCI 1:4 24 MHz or 48 MHz 24.576 MHz or 27.000 MHz or 49.152 MHz 14.318 MHz
Output Buffers Output Buffers
SDCLK SDATA
I2 C Control
Host/2
Output Buffers Output Buffer Output Buffer
24M/48M Select F1 Select 14.31818 MHz crystal XI Crystal Oscillator XO
Fixed Clock
Output Buffer
OE (all outputs) MDS 1492-03 D 1 Revision 020298 Printed 11/15/00
MicroClock Division of ICS*1271 Parkmoor Ave.*San Jose*CA*95126*(408)295-9800tel*(408)295-9818fax
MK1492-03 I C R O C LOC K Intel TM Mobile/SDRAM Clock Source
Pin Assignment
VDD XI XO GND 14.3(OE) SDCLK SDATA HOST1 VDDHOST1,2 HOST2 GND HOST3 HOST4 VDDHOST3,4
PRELIMINARY INFORMATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
F1(PEN) PCI(CSSS) VDD PCI(SEL1) PCI(FS) GND PCIF(LE) 48M/24M(SEL0) VDD HOST6,8(DS) HOST5,7 GND PCISTP# CPUS#
48M/24M Frequency Select Table (MHz)
SEL0 0 1 48M/24M 24.0 48.0
Host/PCI Frequency Select Table
CPUS# 1 1 CSSS X X FS 0 1 OE=M HOST 60.0 66.66 33.33 OE=1 HOST 50.0 75.0 33.33
PCIF Enable Control
PEN 0 M 1 Pin 25 PCI PCI PCIF Pin 24 PCI PCIF PCIF
M
0
X
Output Enable Control Table
OE 0 M, 1 ALL CLOCK OUTPUTS TRISTATED ENABLED
F1 Frequency Select
SEL1 0 M 1 F1 24.576 27.0 49.152 LE 0 1
EMI Control
Low EMI ON OFF
HOST7,8 Enable
DS 0 1 HOST7,8 ENABLED TRISTATED
Power Down Control Table
PCISTP# CPUS# CSSS
1 0 X X X M
1 1 or M M M 0 M
X X 0 1 X X
MODE ON PCI STOP CPU SLOW CPU STOP Power Down PLL STOP
HOST3:8
HOST1,2 PCI
ON U 33MHz ON LOW LOW
ON U 33 MHz LOW LOW LOW
PCIF 48/24 14.3 DESCRIPTION ON ON ON ON All Clocks On. LOW U U U PCI Outputs synchronously enter and leave low state . U 16.6M ON ON Host smooth transition to/from 33 MHz. U ON ON ON Host Outputs synchronously enter and leave low state. LOW LOW LOW LOW All outputs low. PLLs and Oscillator off. LOW LOW LOW ON Oscillator on. PLLs off.
Key: 1 = connected to VDD, 0 = connected to ground, M = VDD/2, X = any valid logic level, U = unchanged (not affected) from previous state. Combination Input/Outputs should be connected to VDD or Ground through a 10 k resistor as shown on page 7.
Pin Descriptions
Pin # Name Type Description 1, 20, 26 VDD P Connect to +3.3V. Must be same voltage on all pins. 2 XI I Crystal connection. Connect to a 14.31818 MHz crystal or input clock. 3 XO O Crystal connection. Connect to a 14.31818 MHz crystal, or leave unconnected for clock. 4, 11, 17, 23 GND P Connect to Ground. 5 14.3(OE) O/TI 14.318 MHz output. Amplitude matches VDD. Tri-State input control for all clocks. 6 SDCLK I I2 C Serial Port Clock 7 SDATA I I2C Serial Port Data 8, 10 HOST 1,2 O Host Output Clocks 1, 2. Amplitude matches VDDHOST1,2. Auto adjusts for low skew at 2.5 V. 9, 14 VDDHOST1,2 or 3,4 P Connect to CPU VDD supply (3.3V or 2.5V). 12, 13, 18 HOST 3,4,5,7 O Host Output Clocks. HOST7,8 enabled by DS input per table above. 15 CPUS# TI CPU Stop power down control; defined in table above. Signal connection on page 7. 16 PCISTP# TI PCI Stop power down control; defined in table above. Signal connection on page 7. 19 HOST6,8(DS) I/O Host Output Clock and DS input. HOST7,8 enabled by DS input per table above. 21 48M/24M(SEL0) I/O Fixed frequency clock and fixed frequency select input per table above. 22 PCIF(LE) I/O PCI Output clock that continues to run in PCI STOP mode. Low EMI enable input. 24 PCI(FS) I/O PCI Output clock, and CPU Frequency Select input. See PCIF and PCI tables above. 25 PCI(SEL1) O/TI PCI Output clock, andSEL1 Select input. See PCIF and F1 tables above. 27 PCI(CSSS) I/O PCI output clock and CPU slow or stop mode select input per table above. 28 F1(PEN) O/TI F1 clock output and PCIF Enable input. Key: I = Input, TI = tri-level input, O = Output, P = Power supply connection, I/O = Input on power up, becomes an Output after 10ms
MDS 1492-03 D
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Revision 020298
Printed 11/15/00
MicroClock Division of ICS*1271 Parkmoor Ave.*San Jose*CA*95126*(408)295-9800tel*(408)295-9818fax
MK1492-03 I C R O C LOC K Intel TM Mobile/SDRAM Clock Source
Electrical Specifications
Parameter Supply voltage, VDD Inputs and Clock Outputs Ambient Operating Temperature Soldering Temperature Storage temperature Operating Voltage, VDD Operating Voltage, VDDHOST1,2 or 3,4 Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH Operating Supply Current, IDD Power Down mode Supply Current Short Circuit Current Input Capacitance Input Frequencies Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle, all MHz clocks HOST3:8 Output to Output Skew Skew of HOST 1,2 with respect to HOST 3:8 PCI Output to Output Skew Lead of HOST outputs with respect to PCI Cycle to Cycle Jitter, CPU Clocks Absolute Clock Period Jitter, Other MHz Clocks EMI reduction, peaks of 5th - 19th odd harmonics Power up time, CPUS# going high to all clocks stable Power on time, applied VDD to all clocks stable
Note 2.
PRELIMINARY INFORMATION
Conditions Referenced to GND Referenced to GND Max of 10 seconds
Minimum
Typical
Maximum 7 VDD+0.5 70 260 150
Units V V C C C V V V V V V V mA mA pF MHz ns ns % ps ps ps ns ps ps dB ms ms
ABSOLUTE MAXIMUM RATINGS (note 2)
-0.5 0 -65 3.0 2 0.8 IOH=-8mA IOL=8mA IOH=-8mA No Load, 66.6MHz Each output 2.4 0.4 VDD-0.4 62 3 50 7 14.318 0.8 to 2.0V 2.0 to 0.8V At 1.5V Rising edges at 1.5V Rising edges at 1.5V Rising edges at 1.5V 1.5 1.5 55 250 250 500 4 250 500 11 20 25 3.3 2.5/3.3
DC CHARACTERISTICS (VDD = 3.3V unless noted)
3.6 VDD
AC CHARACTERISTICS (VDD = 3.3V unless noted)
45
49 to 51
1 -500
1.75
66.6 MHz HOST clock
6 8 12
Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
External Components
The MK1492 requires some inexpensive external components for proper operation. Decoupling capacitors of 0.1F should be connected on each VDD pin to ground, as close to the MK1492 as possible. A series termination resistor of 33 may be used for each clock output. See the discussion on page 7 for other external resistors required for proper I/O operation. The 14.3 MHz oscillator has internal caps that provide the proper load for a parallel resonant crystal with CL=12pF. For tuning with other values of CL, the formula 2*(CL-12) gives the value of each capacitor that should be connected between X1 and ground and X2 and ground.
MDS 1492-03 D
3
Revision 020298
Printed 11/15/00
MicroClock Division of ICS*1271 Parkmoor Ave.*San Jose*CA*95126*(408)295-9800tel*(408)295-9818fax
MK1492-03 I C R O C LOC K Intel TM Mobile/SDRAM Clock Source
Power-On Default Conditions
Input Pin# 5 15 16 19 21 22 24 25 27 28 Function OE CPUS# PCISTP# DS SEL0 LE FS SEL1 CSSS PEN Default M 1 1 1 1 1 1 M 1 M Condition All outputs enabled. HOST clocks running. PCI clocks running. HOST7, HOST8 disabled. 48/24 (pin 21) set to 48 MHz Low EMI function OFF HOST frequency = 66.66 MHz. F1 (pin 28) set to 27 MHz Allows CPU STOP mode. Refer to Power Down Control Table on page 2. PCI (pin 25) set to PCI clock (33.33 MHz). PCI (pin 24) set to PCIF clock (33.33 MHz).
PRELIMINARY INFORMATION
General I 2C Serial Interface Operation
A. The I2C address for the MK1492-03 is D2(hex). For the clock generator to be addressed by an I2C controller, this address must be sent as a start sequence, with an acknowledge bit between each byte as shown below.
MK1492-03 Address (7 bits) + R/W# bit ACK D2(hex)
8 bits dummy Command code
ACK
8 bits dummy Byte count
ACK
Then Bytes 0, 1, 2, 3, 4, 5 in sequence unless a STOP condition is encountered.
B. The MK1492-03 is an I2C slave component only. It does not have any read-back capability. C. The data transfer rate supported by the MK1492-03 is 100K bits/sec (standard mode). D. The input is operating at 3.3 V logic levels (refer to Electrical Specifications Table). E. The data byte format is 8-bit bytes. F. To simplify the I2C interface, the protocol is set to use only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop condition is encountered. G. In the power down mode (CPUS# Low), the SDATA and SCLK pins are tristated and the internal data latches maintain all prior programming information. H. At power-on, all registers are set to a default condition. See Byte 0 detail for its default condition; Bytes 1 through 5 default to a 1 (Enabled output state).
MDS 1492-03 D 4 Revision 020298 Printed 11/15/00
MicroClock Division of ICS*1271 Parkmoor Ave.*San Jose*CA*95126*(408)295-9800tel*(408)295-9818fax
MK1492-03 I C R O C LOC K Intel TM Mobile/SDRAM Clock Source
Serial Configuration Command Bitmaps
Byte 0: Functional and Frequency Select Clock Register (1 = enable, 0 = disable) Note: PD = Power-On Default
Bit 7 6 5 4 3 2 1 0 Pin # -----21 -Description (Reserved) MSB (Reserved) (Reserved) (Reserved) LSB Not used 48/24 MHz (Frequency Select) 1 = 48 MHz, 0 = 24 MHz Bit 1 Bit 0 1 1 - Tri-State all outputs 1 0 - Spread Spectrum for HOST and PCI clocks 0 1 - Normal Operation (Test Mode not supported) 0 0 - Normal Operation PD 0 0 0 0 1 1 0 0
PRELIMINARY INFORMATION
Byte 1: CPU, 24/48 MHz Active/Inactive Register (1 = enable, 0 = disable)
Bit 7 6 5 4 3 2 1 0 Notes: Pin # 28 21 -N/A 10 10 8 8 Name Intel Description F1 48/24 MHz (Active/Inactive) 48M/24M 48/24 MHz (Active/Inactive) -(Reserved) -CPUCLK4 (Active/Inactive) HOST2 CPUCLK3 (Active/Inactive) HOST2 CPUCLK2 (Active/Inactive) HOST1 CPUCLK1 (Active/Inactive) HOST1 CPUCLK0 (Active/Inactive)
Bits 0 and 1 must always be at the same state. Bits 2 and 3 must always be at the same state.
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit 7 6 5 4 3 2 1 0 Pin # -22 N/A N/A N/A 27 25 24 Name -PCIF ---PCI PCI PCI Intel Description (Reserved) PCICLK_F (Active/Inactive) PCICLK5 (Active/Inactive) PCICLK4 (Active/Inactive) PCICLK3 (Active/Inactive) PCICLK2 (Active/Inactive) PCICLK1 (Active/Inactive) PCICLK0 (Active/Inactive)
MDS 1492-03 D
5
Revision 020298
Printed 11/15/00
MicroClock Division of ICS*1271 Parkmoor Ave.*San Jose*CA*95126*(408)295-9800tel*(408)295-9818fax
MK1492-03 I C R O C LOC K Intel TM Mobile/SDRAM Clock Source
Serial Configuration Command Bitmaps (cont.)
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit 7 6 5 4 3 2 1 0 Pin # N/A N/A N/A N/A 19 18 13 12 Name ----HOST6,8 HOST5,7 HOST4 HOST3 Intel Description SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive)
PRELIMINARY INFORMATION
Byte 4: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit 7 6 5 4 3 2 1 0 Pin # N/A N/A N/A N/A N/A N/A N/A N/A Name --------Intel Description SDRAM15 SDRAM14 SDRAM13 SDRAM12 SDRAM11 SDRAM10 SDRAM9 SDRAM8
Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Bit 7 6 5 4 3 2 1 0 Pin # ---N/A --N/A 5 Name -------14.3 Intel Description (Reserved) (Reserved) (Reserved) IOAPIC0 (Reserved) (Reserved) REF1 REF0 (Active/Inactive)
Notes:Inactive means outputs are held LOW and are disabled from switching. Byte 6 is not available on the MK1492-02.
MDS 1492-03 D
6
Revision 020298
Printed 11/15/00
MicroClock Division of ICS*1271 Parkmoor Ave.*San Jose*CA*95126*(408)295-9800tel*(408)295-9818fax
MK1492-03 I C R O C LOC K Intel TM Mobile/SDRAM Clock Source
I/O Structure
The MK1492 provides more functionality in a 28 pin package by using a unique I/O technique. The device checks the status of all I/O pins during power-up. This status (pulled high or low) then determines the frequency selections and power down modes (see the tables on page 2). Within 10ms after power up, the inputs change to outputs and the clocks start up. In the diagrams to the right, the 33 resistors are the normal output termination resistors. The 10k resistor pulls low to generate a logic zero. Internal pull-up resistors (approx. 100k ) are present on DS, SEL0, FS, LE, CPUS#, PCISTP#, and CSSS. Internal resistors on PEN, SEL1, and OE pull to a mid-level (M). The CPUS# input should be connected as shown to implement the 0, M, and 1 selections per the Power Down Control Table on page 2. Contact MicroClock for suggested connections of PCISTP# if the PLL STOP mode will be used. 33
PRELIMINARY INFORMATION
For select = 0 (low)
I/O
10k
to load
Don't stuff for "1" selection
CPU_STOP# 10k
CPUS#
10k
Signals from North Bridge
PWR_DOWN#
Package Outline and Package Dimensions 28 pin SSOP
Inches Symbol Min 0.061 0.008 0.007 0.385 0.150 0.230 Max 0.068 0.012 0.010 0.400 0.160 0.245 0.016 0.016 0.004 0.035 0.01 0.406 0.127 Millimeters Min 1.55 0.203 0.190 3.810 5.840 Max 1.73 0.305 0.254 4.064 6.223 0.410 0.889 0.254 A b c D E
E
H
9.780 10.160
D Q e c b
h x 45 A L
H e h L Q
.025 BSC
0.635 BSC
Ordering Information
Part/Order Number MK1492-03R MK1492-03RTR Marking MK1492-03R MK1492-03R Low EMI Feature Yes Yes Package Temperature 28 pin SSOP 0-70C Add Tape & Reel -
While the information presented herein has been checked for both accuracy and reliability, MicroClock Incorporated assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by MicroClock. MicroClock reserves the right to change any circuitry or specifications without notice. MicroClock does not authorize or warrant any MicroClock product for use in life support devices or critical medical instruments. Pentium is a trademark of Intel Corporation
MDS 1492-03 D
7
Revision 020298
Printed 11/15/00
MicroClock Division of ICS*1271 Parkmoor Ave.*San Jose*CA*95126*(408)295-9800tel*(408)295-9818fax

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